Presently, there are two approaches in realizing short-channel (1 micron) MOS devices employing conventional photolithographic techniques. One approach is the so-called DMOS approach which is described by T. P. Cauge, et al., in an article entitled "DOUBLE-DIFFUSED MOS TRANSISTORS ACHIEVE MICROWAVE GAIN" appearing in Electronics, pp. 99-104, Feb. 15, 1971. The other approach is the VMOS approach described by T. J. Rodgers and J. D. Meindl in an article entitled "VMOS: HIGH-SPEED TTL COMPATIBLE MOS LOGIC" in IEEE J. of Solid State Circuits, Vol. SC-9, pp. 239-249, Oct. 1974. Using these two approaches, the effective source-to-drain spacing of a MOS device is controlled similar to those in which the basewidth of a bipolar transistor is formed, namely by diffusion. Therefore, 1-micron devices can be realized. The speed capability of these devices is greatly enhanced over the conventional MOS devices.
However, the process controllability of the threshold voltage in a DMOS is rather poor, resulting in low production yield. One of the major reasons for poor V.sub.T controllability is that V.sub.T depends on the maximum channel impurity concentration, N.sub.Amax, which is not easily controllable. In a DMOS, the channel is formed by the lateral difference of a successive p-type diffusion -- the channel diffusion, and an n-type diffusion -- the source diffusion made through the same oxide opening. N.sub.amax occurs at the intersection of the source and channel diffusion profiles which have shapes of complementary error function. Any variation in time, temperature or gas flow in either diffusion will vary N.sub.Amax significantly, and therefore V.sub.T. Furthermore, during the channel diffusion, a thin oxide layer is generally grown to keep the surface clean. During the subsequent removal of this oxide layer for source diffusion, an uncertainty in oxide window edges from run to run may occur. Thus an uncertainty in N.sub.Amax will occur correspondingly. Moreover, presently there exists no experimental method by which a lateral diffusion profile can be measured. Therefore, on-process measurement for the diffusion profile subsequent to each high temperature process is not possible. Consequently, LSI DMOS ICs have not been manufactured.
For VMOS, the fabrication process is also complex, requiring tight epitaxial control and seven masking steps instead of four required by conventional p-channel devices. The additional masking steps require etching, aligning, and heating steps, which cause device yield loss due to the probability of inherent misalignments and movement of the diffusion within the device. Furthermore, linear resistors are required as load device, and are known to be inferior to the depletion mode load devices in performance. Moreover, since the substrate of the VMOS is used as common source, only NOR gates can be constructed. Its application, therefore, is limited.
In order to overcome the above-mentioned shortcomings, applicant develop a nonsymmetrical planar double implanted VMOS structure (VDMOS) shown in FIG. 5. The region 74 -- the vertical channel of the VDMOS allows ion-implantation to be used in determining N.sub.Amax and the effective channel directly through accurately controlling the implanting energy and dosage. The fabrication process is also simplified, and the yield enhanced. Furthermore, the VDMOS is a planar device and can allow both enhancement mode or depletion mode devices to be fabricated on the same wafer to be used as load devices.
However, the VDMOS has the following shortcomings: 1), the alignment tolerance for the V-groove definition with respect to the channel is approximately half the length of the V-groove opening. For devices with small V-groove openings, the alignment tolerance would also be small. Any misalignment exceeding the tolerance will cause the device to fail and yield loss; 2), the area shared by the channel and the source region is relatively large, resulting in large source-to-channel capacitance; 3), the channel is non-symmetrical about the V-groove, or with respect to the drain and source; and 4), the fabrication process requires six masking steps.